1. Field of the Invention
The present invention relates to a liquid crystal display device and a fabricating method thereof, more particularly to a liquid crystal display device having a GOLDD (gate overlapped lightly doped drain) type polycrystalline TFT and a fabricating method thereof.
2. Description of the Prior Art
Recently, light-weighted and small-sized flat panel display devices have been actively developed. Among flat panel display devices, the liquid crystal display device has been mass-produced and widely used. One type of liquid crystal display device is a transmission type liquid crystal display device having a TFT (thin film transistor) that is used as a switching device to operate each pixel independently.
In general, a liquid crystal display device includes: a pixel area having plurality of pixels to realize an image; and a driving circuit area for applying various signals to the pixel area. TFTs are formed in both the pixel area and in the driving circuit area. A TFT includes a semiconductor layer forming a channel in which a current flows, a gate electrode for developing an electric field for turning on/off the current flow in the channel according to an applied signal, and a source electrode and a drain electrode for transmitting a data signal to a pixel in accordance with an applied input signal to the gate electrode. As a result of the development of a COG (chip on glass), TFTs have been used to make a more compact liquid crystal display device by forming a polycrystalline TFTs having high field effect mobility in the driving circuit area. The need for high field effect mobility is much greater for the TFTs formed in the driving circuit area than for the TFTs formed in the pixel area. Thus, polycrystalline TFTs are typically formed in the driving circuit area.
Due to the desire for even lighter-weight and smaller-size display devices, there is still a need to reduce the size of a liquid crystal display device. However, it is impossible to reduce the size of the pixel area in which an image is displayed since the size thereof is set to display a desired image size. Therefore, the driving circuit area has to be where a reduction in size takes place. However, when the driving circuit area is reduced, the size of the TFT in the driving circuit area inevitably has to be reduced. A reduction in the size of the TFT means reduction of channel length. The reduction of channel length may cause damage to the channel region due to hot carriers passing through the channel. In addition, the threshold voltage of the TFT may be changed due to hot carriers. A change in the threshold voltage will degrade the quality of a displayed image.
To solve the hot carrier problems, an LDD (lightly doped drain) type TFT is used. The LDD type TFT is fabricated by forming low-density impurity regions adjacent to the channel region and forming a high-density impurity regions separated from the channel region by the low-density impurity regions. In addition, the LDD type TFT prevents leakage current from occurring through the TFT. Because the leakage current or off current of the LDD type TFT is less than that of a general TFT, an LDD type TFT controls signals more efficiently to render a higher quality picture.
Even in an LDD type TFT, there is a limit to how much the channel length can be reduced. The LDD type TFT may not be easily reproducible such that an entire array of TFTs will consistently have the same hot carrier resistance if the channel length gets too short. Over time, the reliability of LDD type TFTs can degrade, especially when the channels are very short. Accordingly, when a TFT is used for a display device having high picture quality and high resolution, such as a HDTV, channel damage may occur due to hot carriers.
To solve the problem of consistency and reliability, a GOLDD (gate overlapped LDD) type TFT has been developed. In the GOLDD type TFT, the gate electrode overlaps the LDD regions or low-density impurity regions of the TFT. Thus, a short channel TFT can be constructed with a high hot carrier resistance such that an array of small-sized TFTs having high reliability can be fabricated.
Hereinafter, processes for fabricating a related art GOLDD type TFT will be described with reference to FIGS. 1A to 1F. First, as shown in FIG. 1A, after forming a buffer layer 102 on a substrate 101 made of a transparent substance, such as glass, a semiconductor layer 103 is formed by laminating amorphous semiconductor, such as silicon, on the buffer layer 102 and etching the amorphous semiconductor. After blocking a region of the semiconductor layer to be a channel region 103a using a photoresist pattern formed on the semiconductor layer, lightly doped source and drain regions 103b are respectively formed by introducing low-density impurities, such as n− type ions, into regions of the semiconductor layer that are not blocked by the photoresist pattern.
As shown in FIG. 1B, after removing the photoresist 104 over the channel region 103a, the amorphous semiconductor layer is crystallized by laser irradiation of the semiconductor layer, and the injected impurity ions are simultaneously activated. As shown in FIG. 1C, a gate insulating layer 105 is formed on the channel region 103a and the lightly doped source and drain regions 103b. A metal layer 106 is then formed on the gate insulating layer 105.
As shown in FIG. 1D, a photoresist is then deposited on the metal layer 106 and patterned by a photolithography process to form a photoresist pattern 107. A gate electrode 106a is formed by etching the metal layer 106 using the photoresist pattern 107 as a mask. The gate electrode 106a is formed to overlap the lightly doped source and drain regions 103b. Next, as shown in FIG. 1E, high-density impurity ions, such as n+ type ions, are injected into the lightly doped source and regions 103b using the gate electrode 106a as a mask. After the high-density impurity ion injection, the outer parts of the lightly doped source and drain regions 103b, which were not blocked by the gate electrode 106a, become highly doped source and drain regions 103c. Accordingly, the gate electrode 106a overlaps the lightly doped source and drain regions that are otherwise known as LDD regions.
After forming the high-density impurity regions or highly doped source and drain regions 103c, as shown in FIG. 1F, a passivation layer 108 is formed over the whole substrate 101. Furthermore, a metal layer is deposited over the passivation layer 108 and etched to form a source electrode 109 and a drain electrode 110. The source electrode 109 and the drain electrode 110 respectively contact the highly doped source and drain regions 103c through contact holes in the passivation layer 108 and in the gate insulating layer 105.
As described-above, two masks are respectively used to inject low-density impurity ions and high-density impurity ions for forming of the GOLDD type TFT. More specifically, a first mask is used to form a photoresist pattern on the semiconductor layer, which is used to inject low-density impurity ions into the semiconductor layer. A second mask is used to form a gate electrode. The gate electrode is then used to block portions of the semiconductor layer already having low-density impurity ions during an injection of high-density impurity ions into other portions of the semiconductor layer in which low-density impurity ions are also already injected. Masks used in photolithography processes are expensive. Accordingly, fabricating costs are expensive when using the two masks of the related art for forming the related art GOLDD type TFT.